Latest Trends in Glass Substrate Technology for AI and HPC Applications

Glass substrates are becoming an important development path for advanced packaging in artificial intelligence (AI) accelerators, high-performance computing (HPC), and other large-package semiconductor systems. The main reason is that glass can provide a highly flat, dimensionally stable platform for large package sizes, fine wiring, high-density interconnects, and embedded optical or electrical functions. At Glass Circuit, we view glass substrate technology as a developing supply-chain opportunity rather than a universal replacement for organic laminates, silicon interposers, or ceramic packages.

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The latest trends include glass core substrates for large packages, finer redistribution layers (RDLs), advanced through-glass vias (TGVs), hybrid optical-electrical packaging, low-loss materials for high-speed signaling, and tighter process integration between substrate manufacturers and semiconductor packaging teams. Buyers should evaluate these trends against package size, I/O density, thermal requirements, electrical performance, yield, qualification status, and expected production volume. Intel describes glass substrates as a potential platform for larger and more advanced packages, while imec is researching glass interposers and glass core technologies for high-density integration.

Why Glass Substrates Matter for AI and HPC Now

AI and HPC processors increasingly depend on multi-die architectures, high-bandwidth memory, advanced interconnects, and large package footprints. As package dimensions and routing requirements increase, substrate warpage, thermal expansion, signal loss, power delivery, and manufacturing yield become more difficult to control. Glass is being investigated because its flatness, dimensional stability, electrical insulation, and compatibility with precision processes may help address several of these challenges.

This technology is especially relevant where a package must connect multiple compute dies, memory stacks, power components, and high-speed interfaces within a limited area. However, the actual benefit depends on the glass composition, thickness, via design, metallization, surface treatment, bonding process, and assembly flow. A glass substrate should therefore be selected as part of a complete package architecture, not as an isolated material decision.

Intel has publicly stated that glass substrates may support larger package sizes and higher interconnect density for future data-center and AI applications. Its 2023 announcement identifies glass substrates as a technology intended for advanced packaging in the latter half of the decade. This indicates strategic industry interest, but it does not mean that every glass substrate design is production-ready for every application.

Source: Intel, “Intel Unveils Glass Substrates for Next-Generation Advanced Packaging.”

Key Trends in Glass Substrate Technology

1. Glass core substrates for larger advanced packages

One of the most important trends is the movement from conventional organic cores toward glass core substrates. A glass core can provide a rigid base for build-up layers and fine-line redistribution structures, potentially improving dimensional control as package dimensions increase. This is relevant to AI and HPC packages because larger packages can experience greater mechanical stress and warpage during lamination, thermal cycling, and assembly.

The engineering objective is not simply to make a larger substrate. The substrate must maintain registration accuracy across the panel, support reliable copper formation, and remain compatible with die attach, molding, underfill, thermal management, and board-level assembly. Buyers should ask suppliers for dimensional tolerance data, warpage measurement methods, panel size options, and process capability studies rather than relying only on a material datasheet.

2. Through-glass vias for vertical interconnection

Through-glass vias, commonly called TGVs, create vertical conductive paths through a glass panel or wafer. They can be formed using laser drilling, mechanical processing, chemical etching, or combinations of these methods, followed by cleaning, metallization, and via filling or lining. TGV technology is being explored for interposers, glass cores, high-density packaging, radio-frequency modules, and optical-electrical integration.

Via diameter, pitch, aspect ratio, taper, sidewall quality, dielectric behavior, and copper reliability all influence the final result. For example, a buyer may compare a 20 micrometer via diameter with a 50 micrometer via diameter, but the smaller opening is not automatically better if it reduces yield or creates voiding during metallization. The correct design depends on routing density, current level, thermal cycling, and the available fabrication process.

imec has published research on glass interposers and TGV-based integration, including work addressing high-density interconnects and heterogeneous packaging. Its research demonstrates the technical direction of the field, although research results should not be interpreted as a guarantee of commercial production performance from every supplier.

Source: imec, research information on glass interposers.

3. Finer redistribution layers and higher wiring density

AI and HPC packages require a large number of connections between compute dies, memory, package substrates, and external systems. Glass substrates are therefore being evaluated as platforms for fine-line redistribution layers and high-density wiring. The relevant specifications include line width, line spacing, pad pitch, via pitch, copper thickness, dielectric thickness, surface roughness, and registration tolerance.

A practical development target may involve line-and-space dimensions below 10 micrometers, but the achievable value depends strongly on the full process stack and whether the design is a prototype, pilot product, or qualified production product. Buyers should request a process design rule document that distinguishes typical capability, guaranteed capability, and experimental capability. This distinction is essential when comparing suppliers.

4. Hybrid optical and electrical packaging

Optical connectivity is another important trend for AI clusters and HPC systems. As electrical links become more difficult to extend at high data rates and reasonable power, co-packaged optics and optical I/O are being investigated as ways to move data between processors, switches, memory systems, and network components. Glass can be attractive in this area because it can provide a stable, transparent, or optically compatible platform for selected photonic structures and alignment features.

Glass does not automatically solve optical packaging challenges. The substrate must be matched with waveguide materials, coupling structures, lasers, photodetectors, connectors, thermal solutions, and contamination controls. A buyer should ask whether the supplier supports only passive glass processing or can also coordinate metallization, optical alignment, TGV fabrication, and assembly interfaces.

The European Commission’s photonics programs and the IEEE’s packaging research community both identify photonic integration and optical interconnects as important areas for future computing systems. These sources support the direction of the trend, but application-specific optical loss and coupling data must be measured on the proposed design.

Sources: Photonics21, European photonics technology roadmap resources; IEEE technical resources on electronics and photonics packaging.

5. Low-loss materials for high-speed signaling

High-speed AI and HPC systems require careful control of insertion loss, return loss, impedance, crosstalk, and power integrity. Glass itself is an electrical insulator, but the complete substrate performance depends on the dielectric formulation, copper surface, conductor geometry, bonding films, RDL materials, and transitions between package and board.

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Material selection should include dielectric constant, dissipation factor, dielectric thickness, copper roughness, moisture absorption, and thermal stability. A low-loss material can be valuable for high-frequency routing, but it may have trade-offs in adhesion, processing temperature, coefficient of thermal expansion, or cost. Buyers should request frequency-dependent electrical data rather than a single nominal dielectric constant.

6. Panel-level manufacturing and process automation

Panel-level manufacturing is being considered to improve material utilization and production economics for large-area substrates. Compared with wafer-based processing, panel formats may offer a larger working area, but they also create challenges in flatness, handling, alignment, cleaning, drilling, lithography, plating, inspection, and singulation.

For B2B sourcing, the key trend is a stronger focus on process control rather than material supply alone. Suppliers need measurement systems for thickness, bow, warp, via geometry, surface defects, copper continuity, and registration. A buyer should also determine whether a supplier has a pilot line, engineering line, or mass-production line, because these stages involve different risk levels.

How These Trends Affect AI and HPC Buyers

The most immediate effect is that substrate selection must begin earlier in the package development cycle. A glass substrate can influence die placement, power delivery, thermal paths, interconnect architecture, assembly equipment, and board design. If the substrate is introduced after the package layout is largely fixed, redesign costs and qualification delays may increase.

Buyers should create a requirements matrix before requesting quotations. Useful inputs include the finished substrate size in millimeters, substrate thickness in micrometers or millimeters, target line-and-space in micrometers, TGV diameter and pitch, copper thickness in micrometers, operating temperature range in degrees Celsius, required lifetime in cycles, and annual volume in units.

Material and Design Options

Glass composition and thermal expansion

Different glass compositions provide different coefficients of thermal expansion, softening temperatures, chemical durability, dielectric properties, and mechanical behavior. A low-CTE glass may be useful for matching silicon or other package materials, but the correct match must be calculated across the complete stack. Silicon has a commonly cited CTE of approximately 2.6 parts per million per degree Celsius, while many glasses are available with different CTE ranges; the supplier must confirm the actual value for the selected grade.

Thermal expansion matching is particularly important during thermal cycling and reflow. The relevant question is not whether a glass has a low CTE in isolation, but whether the glass, copper, dielectric, silicon, underfill, mold compound, and printed circuit board produce acceptable stress together. A finite-element model and representative thermal-cycle testing are normally more reliable than a material-only comparison.

Surface treatment and metallization

Glass surfaces may require cleaning, activation, adhesion promotion, seed-layer deposition, electroless plating, electrolytic copper plating, or other treatments before fine wiring can be formed. Surface energy, roughness, cleanliness, and adhesion influence the reliability of the metal-dielectric interface. Suppliers should explain how they control particles, residues, edge damage, and copper adhesion.

For qualification, request cross-sectional analysis, via-chain continuity data, thermal cycling results, humidity testing where relevant, and failure-analysis capability. If the supplier cannot provide application-specific test data, the buyer should plan a joint engineering validation rather than assuming that standard glass-sheet data is sufficient.

Recommended Supplier Evaluation Framework

Technical capability

First, confirm whether the supplier produces glass substrates, glass cores, TGV components, glass panels, or only raw glass sheets. Then review available thicknesses, panel dimensions, glass grades, via processes, RDL capability, metallization options, inspection equipment, and packaging methods. A supplier with strong glass handling capability may still require a partner for semiconductor-grade redistribution or assembly.

Quality and qualification evidence

Ask for a documented quality plan covering incoming glass inspection, dimensional control, surface defects, via inspection, metal continuity, cleanliness, traceability, and change management. Request actual test reports or representative data where available, and identify which values are guaranteed specifications versus engineering targets. For AI and HPC applications, the qualification plan should connect substrate-level tests with package-level reliability requirements.

Commercial readiness

Cost should be evaluated together with yield, tooling, engineering charges, inspection, packaging, and lead time. A quotation based on a small prototype lot may not predict the price at production volume, especially when TGV drilling, fine-line lithography, or custom glass composition is required. Buyers should request a staged quotation for prototype, pilot, and production quantities, with assumptions clearly stated.

Lead time should be expressed in weeks and separated into material preparation, tooling, process development, first article production, inspection, and shipping. MOQ should also be confirmed for each stage, because prototype MOQ and production MOQ can differ substantially. This approach helps procurement teams compare suppliers on total project risk instead of unit price alone.

Common Mistakes to Avoid

A common mistake is treating glass substrate technology as a drop-in replacement for an organic package substrate. The electrical, mechanical, thermal, and assembly interfaces are different, so a successful design usually requires early co-engineering. Another mistake is specifying aggressive via dimensions or line widths before confirming the supplier’s verified process window.

Buyers should also avoid accepting broad phrases such as “high density,” “high reliability,” or “AI-ready” without measurable definitions. Ask for dimensions, tolerances, frequency conditions, temperature ranges, sample sizes, inspection methods, and test duration. Where evidence is unavailable, classify the item as an open engineering risk rather than a confirmed capability.

What Glass Circuit Can Support

At Glass Circuit, we help B2B buyers organize glass substrate requirements before supplier engagement. We can discuss the intended application, substrate dimensions, glass material preferences, TGV or metallization requirements, surface finish, packaging needs, prototype quantity, and target delivery schedule. The most useful starting point is a technical inquiry containing drawings, specifications, expected annual volume, and the qualification stage.

We do not treat every AI or HPC project as identical. Instead, we recommend matching the manufacturing route to the required performance, volume, tolerance, and budget, while identifying which specifications need additional validation. Depending on the project scope, supplier support may involve material selection, sample preparation, process coordination, inspection documentation, and production sourcing.

Key Takeaways

• Glass substrates are being developed for larger, denser, and more integrated AI and HPC packages.
• The leading technology directions include glass cores, TGVs, fine RDLs, optical-electrical integration, low-loss signaling, and panel-level processing.
• Important buying data includes substrate size, thickness, CTE, line-and-space, via diameter, via pitch, copper thickness, electrical loss, thermal range, MOQ, and lead time.
• Research announcements from Intel and imec demonstrate industry activity, but buyers still need supplier-specific capability and reliability evidence.
• The best supplier is not necessarily the one offering the smallest feature size; it is the one that can control the complete process and provide a credible qualification path.

Conclusion: How to Act on the Latest Glass Substrate Trends

The latest trend in glass substrate technology is a shift toward using glass as an engineered platform for advanced packaging rather than simply as a flat insulating material. For AI and HPC applications, its potential value lies in dimensional stability, large-package support, high-density interconnects, TGV integration, and future optical-electrical packaging. The technology remains application-dependent, and commercial readiness must be verified through measurable supplier data.

As a next step, prepare a one-page specification covering package size, thickness, CTE target, line-and-space, via geometry, electrical requirements, thermal profile, quantity, and qualification schedule. Then ask potential suppliers to identify their proven capability, development capability, test evidence, MOQ, lead time, and remaining technical risks. Contact Glass Circuit with these requirements if you would like to evaluate a suitable glass substrate manufacturing and sourcing route for your AI or HPC project.