Optimizing Wafer Edge Processes For Chip Stacking

Stacking chiplets vertically using short and direct wafer-to-wafer bonds can reduce signal delay to negligible levels, enabling smaller, thinner packages with faster memory/processor speeds and lower power consumption.

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The race is on to implement wafer stacking and die-to-wafer hybrid bonding, now considered essential for stacking logic and memory, 3D NAND, and possibly multi-layer DRAM stacks in HBMs. Vertical stacking allows chipmakers to leapfrog the interconnection pitch from 35µm in copper micro-bumps to 10µm and below.

But going vertical comes at a cost, which has left chipmakers scrambling to find ways to reduce wafer-edge defects. Those defects significantly impede the ability to yield all die on the wafer, and the need to bond wafers together calls for incredibly flat, defect-free 300mm wafers. To better control wafer-edge defects throughout fab processing, and for fusion and hybrid bonding, engineers are fine tuning new and existing processes. These include a symphony of techniques involving both wet and dry etching at the wafer edge, chemical mechanical polishing (CMP), edge deposition, and edge trimming steps.

The improvement in performance and power efficiency is formidable. “Advanced packaging is starting to enable the higher processing speeds and capabilities through chip stacking, bringing memory closer together with the CPU and the GPU, said Alex Smith, executive director of global business operations at Brewer Science. “The shorter that we can make the wires to reach out to get the information and come back and process it, the faster we can accelerate the compute,”

Others agree. “You see that the data movement is still a significant portion of the cost of the chips themselves, so you have these tens or hundreds of cycles of memory access and maybe you have two to four cycles to get the values you want,” said Kenneth Larsen, senior director of product management at Synopsys. “Systems would get a big boost if we can get the memories much closer to the processors. And there is a tremendous savings in energy consumption when sending signals up and down the stack, instead of the long drives to send signals from the chip to external memory and back again.”

Processes also are being crafted around the specific needs of advanced packaging. For example, Lam Research and its partner CEA-Leti optimized an edge deposition process for advanced packaging applications, which was rolled out last year. Prior to wafer thinning, edge deposition on bonded wafers provides reinforcement.

“These structures require material to fill in the gap at the edge, so the deposited film acts as a supporting layer,” said Ian Latchford, product marketing director at Lam Research. “Otherwise, the device wafer can crack at the edge during CMP because removal is faster at the edge. So there is a slope called CMP roll-off on the wafers that causes a gap to form between the wafers, which goes to zero. Without edge deposition, cracking at the wafer edge can occur during wafer thinning, dramatically impacting yield.”

Using AI-based advanced process control (APC) software, engineers can improve uniformity analyses across the entire wafer as well as wafer-to-wafer within a stack.  “We provide real-time APC of plasma confinement center-to-edge, films uniformity center-to-edge, litho processes center-to-edge, etc.,” said Boyd Finlay, director of solutions engineering at Tignis. “We also analyze multiple wafers stacked on top of one another and sliced by time, recipe, tool, chamber, or technology.”

Wafers prepared for hybrid bonding must meet critical process specs to create high yielding hybrid bonds, such as incredible flatness (<1nm center-to-edge non-uniformity), zero particles on wafers to be bonded, exceptional wafer/wafer or die/wafer alignment, <200nm die placement accuracy, and more. Edge defects include particles, chipping, scratches, thin-film peeling, damage from wafer handling, which can dislodge and become defects that affect product yield.

CMP challenges
First developed by IBM in the late s for the introduction of copper damascene interconnects, CMP has been a huge enabler for planarizing wafers and packing more functions into devices in a thinner profile. Wafer flatness, controlled edge roll-off, and particle reduction are key goals of CMP. Now, in addition to CMP’s use in planarizing shallow trench isolation, dielectrics and copper in BEOL interconnects, wafer grinding and CMP are being optimized to drastically thin the 300mm silicon wafer backside after bonding.

The quality of the device wafer also depends on the quality of starting silicon.  “Processing the edge of the wafer has been an issue for many years,” said Mike Walden, senior director of market research and analytics at TECHCET. “There’s a discontinuance or abrupt change that occurs because there is no neighboring material beyond the edge, so it changes the physics in those regions. In the polishing of bare silicon wafers, we’ve taken steps to try to compensate, such as using retainer rings. In this CMP, you have a retainer ring that supports the wafer in the polishing nest. That wafer edge is only contacting a very small amount of the ring, and the bare silicon wafer edge is essentially shaped into three sections — a taper, a more blunt edge and then another taper, which proved ideal for improving CMP performance versus a more rounded edge.”

Throughput is vitally important to all wafer processes. “If you perform CMP too fast you’re going to introduce non-uniformities, and you have a higher potential for introducing mechanical damage,” Walden said. “So there’s a very delicate tradeoff between maximizing the removal rate but keeping the uniformity and defectivity in check.”

CMP tool suppliers such as Applied Materials, Ebara Technologies, and Axus Technology, together with pad and slurry providers, optimize wafer and wafer-wafer uniformity for each application, such as copper CMP in BEOL interconnects. “They design the entire consumables kit (slurry, pad, conditioner disk, P-CMP cleaner) at the same time for target process applications,” said Tignis’ Finlay. “The tools are also controlled for conditioner arm sweep rates versus pad lifetime and versus pad diameter.”

Chemical and mechanical engineering consider the tool, pad, and slurry combinations. “There are various characteristics that you control on the CMP pad including stiffness or hardness. The particle size, distribution and composition are extremely important, because these determine, in part, how the rate of removal is going to occur across the wafer and from wafer to wafer,” said Walden. He added that surface pattern engineering and optimized pad conditioning techniques also are used, as is real-time sensing and feedback of the pad surface so users can adjust CMP processes on the fly and make corrections.”

Both CMP and wet/dry etching processes are optimized to remove wafer edge defects using dedicated tools.

Dry and wet etching
“Bevel etching has been in production for about 15 years to enable yield enhancement by removing any undesirable materials — things that cause damage to the wafers or particles defects that can move from the bevel onto the center of the wafer,” said Lam’s Latchford. “Customers implement bevel etch throughout the line because there are certain points in a process flow where things build up.”

The etcher is optimized to remove any type of film on the edge of the wafer, whether it is a dielectric, metal, or organic. During reactive ion etch (RIE) of the bevel, the wafer is held by a top and bottom plate so that only the wafer edge, bevel, and backside edge of the wafer are exposed.

The etcher process is used in different ways, depending on the customer and specific flow. “Some customers wait until they’ve got a stack of films built up, and then kind of clean it back to the silicon surface. Other times they just try to get rid of one layer, like a thick carbon hard mask that is used for deep etches in NAND flows,” explained Latchford. This carbon mask is also conductive and can lead to arcing in the RIE chamber, so it is best removed.

“If you have 500 or 800 steps in a process flow, there are typically certain places where films build up or surfaces become roughened,” he said. “So there’s some contamination potential that we’re solving with bevel etch.”

And even though wet and dry cleaning processes have their own particular strengths, device makers typically choose one or the other for high-volume production. “People have been trying to clean edge defects and the bevel for 20 years,” said Sally Ann Henry, chief technologist of ACM Research. “Obviously, as we’ve moved down in technology nodes, it’s become more of an issue because people want to get more good die from the edge of the wafer. We have an edge exclusion of 2mm currently, and customers would prefer 1mm, so the defects on the edge of the wafer become more and more important.”

To successfully handle these thin wafers during and after the final grinding/thinning steps, the device wafer is first bonded to a glass wafer or silicon carrier wafer that meets semiconductor industry standards for prime wafers. Before the bonding step, these wafers will pass through at least one CMP processing step, the associated post-CMP, pre-bond cleaning steps, and the bonding process itself. If these steps do not meet critical quality, voids in the bonded wafers can occur at the edge and perhaps throughout the mating surfaces.

“If you’ve got a silicon oxynitride film, for instance, you may get peeling because there’s weak adhesion on the bevel,” Henry said. “You can clean that off with DHF. If you have something like titanium nitride (TiN), you can get peeling from the thermal stress, so it can be cleaned off with SC1, and you have similar applications for removing a backside polymer. After plasma etching of a film, you get polymers on the edge of the backside. You also can get peeling post-CMP. You want to remove that to prevent the peeled portion from re-depositing on the front of your wafer, causing a defect and killing the device.”

A dedicated cleaner provides edge etch. “We have a bevel clean system where we center the wafer, and then we use very small volumes of chemistry to clean the edge of the wafer, the outer 1.05mm using the traditional chemistries — SC1, dilute HF, SPM (sulfuric-peroxide mixture), or maybe a mixture of HF and nitric acid, depending on what film you’re trying to remove,” she said. “The chemistry is applied through a small nozzle while the wafer spins, using nitrogen on the top of the wafer to control that bevel edge clean with high accuracy.”

Because thin wafer handling and processing is such a challenge, most chipmakers use temporary bonding of wafers to glass wafers for support during processing. “Most people are bonding to a glass wafer. And in most of our tools, we clean the wafer front side and the back side at the same time,” said Henry. “So for some of these very thin applications, particularly where you’ve thinned the wafer down to maybe only 200µm thick, customers use a Tyco ring that holds the wafer because bowing is the biggest problem.”

Current state-of-the-art involves using glass wafer carriers for the bond/debond of thin wafers, where an organic adhesive bonds the wafer to the glass, which is later removed using laser or UV debonding processes. These processes are compatible with wafer-to-wafer or die-to-wafer processing using collective processing. A variety of adhesives are available to be compatible with either high temperature or lower temperature wafer processing.

“Brewer Science’s expertise is in the thin wafer handling process for temporary bonding and debonding,” said Smith. “What is interesting is that 10 years ago, if you debonded a wafer and cleaned it, you then checked it with a microscope and if there was no residue that was you’re like, ‘Okay, I’m good.’ But now the cleanliness requirements have really accelerated with hybrid bonding. Because if you have any particulates at all is a potential yield killer,” said Smith.

Dry deposition
NAND devices were the first critical application for which Lam developed its bevel deposition (see figures 1 and 2). “The bevel deposition system deposits a protective silicon dioxide layer, and we first started working on edge deposition for 3D NAND devices,” Latchford said. “It’s now expanded to other applications. One of the most interesting uses is enabling bonded wafer applications for 3D packaging. The deposition can occur over the first few millimeters on the front side, bevel, and/or the back side, from a few hundred angstroms of thickness to microns of material.”

Lam’s system is built on learning from its bevel etch tools and other lines of deposition systems. “We took a lot of the key IP and capability established in the bevel etch system, like the best-in-class precision wafer centering and plasma shaping technology, and applied it to the edge deposition system introduced last year.”

Fig. 1: The Coronus DX process deposits a silicon dioxide film concentrated on the bevel area. Source: Lam Research 

Another new application, which is in R&D today, involves depositing thin silicon nitride film to control copper contamination. For the existing applications, Lam engineers expect a 0.2% to 0.5% yield boost per step.

Fig. 2: Schematic of bevel deposition system (left), and process flow for bevel deposition, bonding, and thinning flow. Source: Lam Research/CEA-Leti

Wafer thinning and edge trim
Wafer thinning of the base silicon for advanced devices induces significant stress. “When we thin it down, the underlying silicon becomes thinner and thinner, and so multiple thermal and mechanical stress are revealed as deformation,” said Shaun Bowers, senior market analyst for semiconductor packaging and materials at TECHCET. “For NAND and advanced logic devices, for instance, there is very little silicon left. The rest of it is all the metal stacks, and all those layers add to the stress.”

To provide an idea of just how much silicon is removed, one must consider the original wafer. “For 300mm silicon wafers, you start with 775 microns, and after you’ve done with all your device processing, you’re thinning it to 35 to 50 micron,” said Walden.  “And particularly as you start to think about this concept of compute-in-memory, where you’re going to stack logic right on top of very high-performance, high-bandwidth memory, you have completely different devices with completely different forces and stresses that exist between those two.”

The edge trimming process is a wet process that can remove the outer 1 to 1.5mm of the wafer, and it can be performed either pre-bond or at the bonding step. “There are different opinions about that. But say you are doing fusion bonding, every wafer has CMP roll-off, and then there’s basically the bevel,” said Thomas Uhrmann, director of business development at EV Group. “So if you bond together, there always will be a region that is not perfectly filled. There is basically a very, very small gap that gets slowly to zero. If you now start to grind it down, it starts to get very brittle in this area because the trim is basically like a knife. So this edge control and how you manage it is a hot topic right now.”

Others agree. “There can be two major yield fallouts in bonding due to stress depending on format,” said Bowers. “In chip-to-wafer bonding, the bumps on the edge of the chip are very susceptible to stress. Designers have to alter the design rules to pull I/Os into the center of the chip if they cannot alter the stress profile. In wafer-to-wafer bonding for an HBM, for instance, the bumps at the wafer periphery are most at risk for stress. And you’ve got a chamfer at the edge that is hard to control, and you may have some edge damage magnified by stress. People are looking at different ways to solve that.”

Wafer edge trimming is performed prior to wafer-to-wafer bonding, bulk silicon removal, and CMP. Many of the traditional CMP suppliers offer edge trimming processes.

Conclusion
Wafer edge defects are a substantial challenge in manufacturing that are being addressed using CMP, dry or wet etch, edge deposition, and wafer edge trimming. Even though hybrid bonding is being used in production by some leading device makers, it is still a relatively immature and costly process. By improving and optimizing the processes specifically for wafer stacking, more segments of the industry will be able to access this enabling technology.

Brewer Science’s Smith points to one potential improvement. “For hybrid bonding you want to thin the wafer and then release it. Then you’re going to bond it either chip-to-wafer or wafer-to-wafer. So you’re still thinning the wafer, first de-bonding it and needing to clean it. And there are some mechanisms where you would like to bond wafer-to-wafer and then do the thinning, but that remains to be seen how that plays out. I’m sure that eventually we’ll be able to do those things directly to eliminate a process step,” he said.

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Defect Challenges Grow At The Wafer Edge

Gearing Up For Hybrid Bonding

Wafer cleaning, once a rather mundane task as simple as dipping wafers in cleaning fluid, is emerging as one of the top major engineering challenges for manufacturing GAA FETs and 3D-ICs.

With these new 3D structures — some on the horizon but some already in high-volume manufacturing — semiconductor wafer equipment and materials suppliers in the wet cleaning business are at the epicenter of a push for increased yield and reliability. Cleaning logic and memory structures used to be straightforward. But starting with finFETs, and moving next into gate-all-around (GAA) structures, as well as advanced DRAM capacitors and 3D NAND, cleaning has entered a third — and not always visible nor measurable — dimension.

Goto Microtreat to know more.

Cleaning steps are found throughout the semiconductor manufacturing process, and there are hundreds of them. They involve not just cleaning, but making sure the surface is prepared for the next step in photoresist, post-etch and implant strip, general cleaning, and backside cleaning for multiple patterning and EUV, notes Sally-Ann Henry, director of business development at ACM Research. What was once a bath in a wet bench has evolved into innovative single-wafer cleaning solutions for the advanced nodes.

“As new materials and process architectures are introduced into an already complex manufacturing process, a specialized cleaning process is the key to further innovation,” said Brian Wilbur, director, Semiconductor Products Diversification at Brewer Science. He described the company’s customized approach to cleaning. For instance, Brewer’s selective surface modification materials can provide high selectivity to metals, polymers, dielectrics, etc., to enhance cleaning solutions.

“As scaling continues, features are getting smaller and more complex, and chipmakers are exploring new materials. This is making achieving precise, uniform cleaning more challenging,” said David Kretz, senior director of key account technology for Lam Research’s Clean Product Line. “New approaches are needed for advanced next-generation logic, DRAM, and NAND. As cleaning processes are also used multiple times in the chip-making process to remove yield-limiting residue and defects, the need for cost-effective, highly efficient processes is even greater.”

The market for Wet Wafer Processing Systems is slightly more than $5B, according to TechInsights. The top three companies — in order: Screen Semiconductor Solutions, and Lam — account for about 75% of the market. The next three — Semes, Naura, and ACM Research — account for another 20%. Despite the dominance of the top three, Risto Puhakka, president of VLSI Research (now part of TechInsights), describes the marketplace as “fairly competitive.” Like much of the equipment market, the wet clean equipment market saw big upswings over the last couple of years, reaching growth of more than 40% in . The firm sees it dropping to -7% in , but picking up again with an AAGR in to of 8.3%.

Fig. 1: The EOS wet clean system delivers low on-wafer defectivity and high throughput to address demanding wafer cleaning applications. Source: Lam Research

3D structures
The challenges are somewhat different for logic versus memory structures. At Semicon West , Ian Brown, vice president, engineering at Screen, gave a detailed talk entitled, “Unique Challenges Associated with Manufacturing 3D Devices and Structures Including GAA, 3D DRAM, and 3D NAND and Wafer Cleaning Technology in 3D Integrated Circuit Devices.” (The video is available here.)

Consider logic devices. While cleaning for finFETs in high-volume manufacturing no longer presents any particular difficulties, the impending move to GAA structures — first nanosheets and later forksheets — is rife with challenges.

“The big challenge is the hidden surfaces,” said Brown. “How do I clean etch a surface I cannot see?” The confined, hidden vertical surfaces are especially tough. In nanosheets, six vertical surfaces are hidden, and in forksheet FETs that number rises to sixteen.

New materials also are being added, which raise complications for selectivity. The industry is looking at new wet chemistry options, vapor etch, or some combination therein.

But with the arrival of nanosheets, Brown said the new consideration is pattern collapse. This phenomena was encountered previously with 3D NAND, so some of that learning can be applied to the new logic structures.

Fig. 2: New logic structures will require new cleaning solutions. Source: Screen Semiconductor/SEMI

In memory structures, both 3D NAND and deep DRAM capacitors present challenges. In 3D NAND, the number of cell layers keeps increasing. Micron recently announced it has reached 232 layers. That makes etching uniformity down the pillars very critical. “You know, it’s very easy to over-etch these things because you’re targeting a uniform edge top to bottom,” Brown observed. “And the performance of these devices requires a uniform edge in the vertical direction.”

A lot of work has been done over the last five years, but this remains difficult. “As part of the scaling of 3D NAND, the aspect ratio of these horizontal lines is getting more challenging,” he said. “And even today, we have pattern collapse in the horizontal direction.

While the industry has long dealt with vertical pattern collapse, the challenge is now the aspect ratio in the horizontal direction. The industry is working on solving that problem to bring this technology into high-volume manufacturing.

Fig. 3: 3D NAND poses new cleaning challenges. Source: Screen/SEMI

Defect removal
Defect removal was once just a case of etching the surface and soaking the wafers in a wet bench bath, releasing the particles so they floated away. That cost-effective approach worked up to around 90nm, and it had extremely high throughput. However, after 90nm, other solutions were also needed. Wafers were cleaned individually using a dual-fluid spray system. As particles became smaller, more dispersed, and harder to detach, the spray condition was tuned. But that only will go so far before the spray pressure causes structural damage.

Furthermore, the tiny spray droplets are still about a micron in size — often twice the size of the trenches they need to clean in advanced 3D structures. And with GAA structures, there is no line of sight, so the sprays can’t even access hidden surfaces.

Researchers in the industry are now looking at polymers to help remove particles. A polymer film is spun on and then peeled off away in a structured fashion, taking particles with it. Screen’s version of this is called Nanolift.

Backside wafer contamination and wafer warping also have become general issues in advanced technology nodes. Particles left on the back of the wafer can throw off lithography.

Fig. 4: The SB- single-wafer backside cleaning system. Through a combination of a spray and brush cleaning, the tool mechanically removes backside contaminants, precisely etches backside layers and removes wafer edge residues, while minimizing wafer warpage. Source: Screen

Prior to 65nm, a popular wet cleaning technology was megasonics, which uses very high frequency sonic waves to create oscillating bubbles that gently scrub the structure. But after 65nm, the industry moved away from megasonics, because popping bubbles can damage delicate structures.

ACM Research brought megasonics back to the fore a few years ago with the introduction of highly controlled bubbles, making it appropriate for the current range of advanced structures with hard-to-reach areas. The Smart Megasonix technology allow chemicals to enter deep holes in 3D structures, followed by the company’s hot IPA vapor dryer. The success is in the numbers. ACM posted nearly 75% year-over-year growth from to . It’s Space Alternated Phase Shift (SAPS) technology employs alternating phases of megasonic waves to deliver megasonic energy to flat and patterned wafer surfaces in a highly uniform manner on a microscopic level. The bubbles are allowed to burst, but in a very controlled way, so they remove random defects across the wafer much more efficiently than conventional jet spray processes, according to the company.

For even more delicate structures, ACM’s Timely Energized Bubble Oscillation (TEBO) technology enables precise, multi-parameter control of bubble cavitation during megasonic cleaning by using a sequence of rapid pressure changes to force bubbles to oscillate in specific sizes and shapes. And because these bubbles oscillate but don’t burst, TEBO technology avoids feature damage, making it a good fit for advanced 3D structures and devices with very high aspect ratios.

Drying
After each cleaning step, there is a drying step. In advanced 3D structures, that drying step creates greater risks of pattern collapse. In logic, the risk occurs in post STI etch, post poly etch, nanosheet release, and nanowire release. In 3D NAND, the risk of collapse comes during the silicon nitride pullback used to create what looks like a “staircase.”

Fig. 5: The Cellesta -i MD 300mm single-wafer clean system targets ≤10nm nodes. The system enables thorough cleaning without damage to the well-patterned wafer surface including particle removal. Pattern collapse-free drying technology utilizes chamber atmosphere control and an improved IPA dispenser. Chemical recycling improves productivity and running cost. Source:

DRAM capacitors are currently the biggest challenge due to the aggressive aspect ratios.

Drying processes using spin, isopropyl alcohol (IPA), and some N2 drying carried the industry through the 2D epoch. But advanced 3D structures now rely on more and more IPA drying steps. While this is not a new process, says Brown, said more IPA drying creates greater volatile organic compound (VOC) emissions from fabs. Most of the cleaning vendors and suppliers are now tackling that in partnership with their customers.

Currently for finFETs, IPA drying with surface modification is the state-of-the-art. But with more advanced 3D structures, the surface tension of the liquid can increase the risk of pattern collapse. The next option is sublimation, which eliminates the liquid phase transition altogether by going directly from a solid to a gas.

The next drying option beyond sublimation is super-critical carbon dioxide (SC-CO2), in which the properties of the CO2 are midway between a gas and a liquid. While it is currently in use by some chipmakers, it is a relatively slow process that involves much higher pressure and energy for heating — all adding up to much higher costs. Brown reckons that the ongoing work to extend IPA drying and sublimation ultimately will prove more cost-effective for most HVM.

Etch uniformity
In 2D, uniformity was a question of within-wafer or wafer-to-wafer. But in 3D NAND, the uniformity of the etch creates the gate, so the device performance is very strongly dependent on etch uniformity. The etch at the top, middle and bottom needs to be uniform. A straight profile is required for the liner and recess metal. “These are fun problems to work on,” and some of the industry’s best minds are working on it, Brown said.

There are a few approaches to improving wet etching. The mass transport on the emulsion tools can be improved, or the switch can be made from immersion tools to single-wafer tools. Other alternatives include vapor etch or a combination of wet and vapor etch. To study the controlling of wet chemistry in narrow spaces, the industry has turned to advanced simulation to understand the fundamentals of the processes. The chemical suppliers also are devising creative solutions to enhance control.

Environmental concerns
Companies in the cleaning equipment and materials business are on the front line of environmental and sustainability concerns, so are looking for ways to reduce the chemical and water usage as well as the exhaust emissions of their equipment.

Fig. 6: The Tahoe tool combines batch and single wafer cleaning with optional megasonics in one platform. It can reduce sulfuric acid usage and chemical waste by 80% compared to single wafer systems. Source: ACM Research

and Screen are among those that have joined imec’s Sustainable Semiconductor Technologies and Systems (SSTS) research program, which supports the semiconductor industry in reducing its carbon footprint.

All the major players are looking for ways to reduce sulfuric acid use (one of the most widely used chemicals in the industry), as well as other chemicals. Screen, for example, has developed a sulfuric peroxide mixture (SPM) reclaim function on their single-wafer SU- platform, where the 70% of the dispense volume of H2SO4 can be reclaimed, and an optional exhaust recirculation system can reduce emissions by 65%. The company is targeting a 20% reduction in greenhouse gas emissions from the use of sold products by .

Chipmakers also are doing their part to decrease the environmental footprint of advanced structure cleaning processes. UMC, for example, has been working with chemical suppliers to develop greener, less toxic chemicals, many of which have now been deployed in their fabs.

“This will continue to be challenging as fabrication technologies become increasingly complex, customers’ designs become more sophisticated, and new materials are introduced,” said Chun-lung Chen, a director in UMC’s Technology Development Module Division who oversees advanced development of etching and cleaning processes. “Enhancing the efficiency of cleaning solvents and reducing the environmental impact of chemicals used in the cleaning processes used to be viewed separately, but the two challenges are converging. Whether required by customers, regulatory requirements, or internal ESG targets, the trend is moving toward greener solutions and less waste.”

This represents a big shift for foundries. “At UMC, we first focus on reducing etching waste, or adjusting the residue composition so that it is easier to remove,” he said. “We then work on optimizing the formula, concentration, and temperature of solvents in order to achieve greater cleaning efficiency. More wafers can be produced using the same amount of chemicals, which brings down costs and generates less hazardous waste.”

The metrology gap
“If you can’t measure it, how well do you know how you’re performing?” asks Brown. Trying new solutions during the development process then having to wait days for a SEM to come back and tell them if they are on the right track is frustrating.

Mark Thirsk, managing partner at Linx Consulting, calls it the metrology gap. “Metrology systems are not able to measure the contamination levels and particle sizes that are critical,” said Thirsk, whose company provides strategic consulting and market analysis services to chemical, gas and materials suppliers in the electronics supply chain. Linx puts the “formulated cleans” market — the chemicals used to remove residues post-etch and post-CMP — at $560 million, with a CAGR of 5% through .

A contaminant of just a few nanometers won’t show up on standard in-line metrology equipment. It requires a SEM image to find it, which is not practical in a high-volume manufacturing environment, Thirsk noted. “We’re asking the cleaning companies or the chemical companies or the equipment companies to control beyond where we can measure,” he said. And that’s a problem that’s yet to be solved.

For its part, KLA points to solutions for identifying contaminants on unpatterned wafers for wafer and process tool qualification, on patterned wafers for inline monitoring of after clean processes, and to chemistry process control products used to qualify the incoming chemicals. “KLA works in close collaboration with our customers and partners across the semiconductor ecosystem to understand their next-generation challenges,” said Ming Li, senior marketing director of the Surfscan and ADE Division at KLA. “This information drives our technology roadmap, so that we are producing products capable of addressing chip manufacturers’ most critical challenges at the right time.”

Conclusion
Cleaning is critical to yield and reliability. New 3D structures have added many new challenges. Leaders in cleaning technologies are working on innovative solutions, but some particular problems, like the lack of the line-of-sight and the metrology gap, remain unsolved.

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